Download ARM Assembly Language Programming by Peter J Cockerell PDF

By Peter J Cockerell

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The eight status bits of R15 are seen as zeros by the ALU, and so they don't figure in the addition. Remember also that the value of the PC that is presented to the ALU during the addition is eight greater than the address of the ADD itself, because of pipelining (this is described in more detail below). In the instruction MOV R0,R15,ROR #26 all 32 bits of R15 are used, as this time the register is being used in an position. The effect of this instruction is to obtain the eight status bits in the least significant byte of R0.

See the section 'Using R15 in group one instructions' below. Examples: TST R0,R5 ;Test bits using r5, setting flags TST R0,#&20 ;Test case of character in R0 ORR Logical OR The ORR instruction produces the bit-wise OR of its operands. The OR of two bits is 1 if either or both of the bits is 1, as summarised below: OR 0 0 0 0 1 1 1 0 1 1 1 1 In the ARM ORR instruction, this operation is applied to all bits in the operands. That is, bit 0 of the is ORed with bit 0 of the and stored in bit 0 of the , and so on.

To get around this and related problems, the immediate operand is split into two fields, called the position (the top four bits) and the value (stored in the lower eight bits). The value is an eight bit number representing 256 possible combinations. The position is a four bit field which determines where in the 32-bit word the value lies. Below is a diagram showing how the sixteen values of the position determine where the value goes. The bits of the value part are shown as 0, 1, 2 etc. The way of describing this succinctly is to say that the value is rotated by 2*position bits to the right within the 32-bit word.

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